View EV1320QI-E_5157576.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ev1320qi 2 a source/sink ddr memory termination converter w ww.enpirion.com description the ev1320qi is a dc to dc converter specifically d esigned for memory termination applications. the device offers high efficiency, up to 96%, while providing a solution footprint similar to that of a linear termination device. the ev1320qi comes in a 3mm x 3mm x 0.55mm qfn 16-pin package and requires only a small number of external mlcc capacitors. the device is designed to operate directly from the vddq supply rail. no external divider or reference is required. the ev1320qi provides a very stable output voltage (vtt) which tracks vddq while sinking and sourcing up to 2a of continuous output current. up to 4 ev1320qi devices can be paralleled to source up to 8a of current. an enable pin with output discharge is available for s3 (suspend to ram) states. ev1320qi is specifically designed to meet the precise voltage, fast transient requirements of present and future high-performance, ddr2, ddr3, and low power ddr4 jedec vtt requirements. advanced circuit techniques and high switching frequency deliver high-quality, compact, non-isolated dc-dc conversion. features ? high efficiency, up to 96% ? 40mm 2 total solution size ? no external inductor required ? jedec compliant ddr2/3/qdr and low power ddr 4 solution ? enable pin with output discharge to support s3 (suspend to ram) mode ? operates directly from vddq ? vout (vtt) voltage tracks vddq/2 40mv ? source and sink up to 2a continuous current ? parallel up to 4 devices for 8a vtt current ? programmable soft start/soft shutdown ? cost effective integrated solution ? thermal overload, over current, short circuit, and under-voltage protection ? rohs compliant, msl level 3, 260c reflow applications ? vtt bus termination for ddr2, ddr3, low power ddr4, and qdr memories figure 1 . simplified applications circuit figure 2. highest efficiency in smallest solution size 80 82 84 86 88 90 92 94 96 98 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 efficiency (%) output current (a) efficiency vs. output current vtt = 0.9v vtt = 0.75v vtt = 0.6v conditions av in = 3.0v v ddq = 2* vtt 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 2 ordering information part number package markings temp rating (c) package description ev1320qi ev1320qi -40 to +85 16-pin (3mm x 3mm x 0.55mm) qfn t&r EV1320QI-E ev1320qi qfn evaluation board pin assignments (top view) pgnd pgnd vddq vddq figure 3: pin out diagram (top view) note a : shaded area highlights exposed metal below the package that is not to be mechanically or electrically connected to the pcb. refer to figure 10 for details. note b : white ?dot? on top left is pin 1 indicator on top of the device package. pin description pin name function 1 nc this pin is internally not connected. may be used as part of the vddq copper to optimize the layout. otherwise, leave this pin open. see figure 9. 2 avin input supply for internal controller and protection circuitry 3 enable input enable. applying a logic high enables the output and initiates a soft-start. applying a logic low disables and discharges the output. enable is internally tied to avin and ground through a 100k resistor divider. leaving enable floating will result in voltage at half of avin. 4 pok vtt ok flag. this is an open drain output usually pulled up to avin. leave floating if unused. 5 ss soft start pin. connect soft start capacitor between this pin and agnd. 6 agnd quiet ground for analog circuitry. connect to the ground plane with a via next to the pin. 7, 8 pgnd power ground. connect these pins to the ground electrode of the input and output filter capacitors. see layout recommendations for more details. 9,10 c1n place 1 x 22f and 1 x 10f x5r mlcc capacitors between c1n and c1p. 11,12 vout vtt voltage = ? vddq. 13,14 c1p place 1 x 22f and 1 x 10f x5r mlcc capacitors between c1n and c1p. 15,16 vddq vddq voltage; vout (vtt) tracks this voltage. 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 3 absolute maximum ratings caution : absolute maximum ratings are stress ratings only. functional operation beyond the recommended operating conditions is not implied. stress beyond the absolute maximum ratings may impair device life. exposure to absolute maximum rated conditions for extended periods may affect device reliability. parameter symbol min max units voltage on avin -0.5 4.0 v voltage on c1p, c1n -0.5 2.0 v voltage on agnd, pgnd -0.5 avin + 0.3 v voltage on vddq -0.5 2.2 v voltage on vout -0.5 vddq + 0.3 v voltage on pok -0.5 avin + 0.3 v voltage on ss -0.5 avin + 0.3 v voltage on enable -0.5 avin + 0.3 v storage temperature range tstg -65 150 c maximum operating junction temperature tj-abs max 150 c reflow temp, 10 sec, msl3 jedec j-std-020a 260 c esd rating (based on human body model): all pins 2000 v esd rating (based on charged device model) 500 v recommended operating conditions parameter symbol min max units operating junction temperature t j -40 +125 c operating ambient temperature t a -40 +85 c thermal characteristics parameter symbol typ units thermal resistance: junction to ambient (0 lfm) (note 1) ja 50 c/w thermal shutdown t sd 150 c thermal shutdown hysteresis t sdh 25 c note 1 : based on 2oz. external copper layers and proper thermal design in line with eij/jedec jesd51-7 standard for high thermal conductivity boards. 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 4 electrical characteristics note: avin = 3.3v; vddq = 1.5v. minimum and maximum values are over operating ambient temperature range unless otherwise noted. typical values are at t a = 25c. parameter symbol test conditions min typ max units vddq voltage range vddq 0.95 1.5 1.8 v avin voltage range avin 3.0 3.3 3.465 v vtt tracking accuracy dc (note 2) vtt avin=3.3v5% 0a i vtt 2a 0.49* vddq ? 40 0.51* vddq + 40 mv under voltage lockout; avin rising v uvlo 2.5 v under voltage lockout; avin falling v uvlo 2.2 v avin shut-down supply current i s enable=low 600 a vddq shut-down supply current i s enable=low 200 a avin no load operating current i avin avin=3.3v 6 ma vddq no load operating current i vddq avin=3.3v 750 a switching frequency f sw 500 625 750 khz pok threshold sourcing current v out rising 95 % pok threshold sourcing current v out falling 85 % pok low voltage i sink = 1ma 0.15 0.4 v pok pin v oh leakage current avin = 3.3v pok high 25 a output impedance r out ? v out /? i load 20 m continuous output current; i _max_source vddq=1.5v avin=3.3v -2 2 a over current trip level i ocp avin=3.3v 4.5 a enable threshold logic low ena_vil max voltage to ensure the converter is disabled 0.3 v enable threshold logic high ena_vih 3.0v avin 3.46v avin ? 0.5 avin v enable input current 100 200 a note 2 : as measured at the bulk capacitors at the edge of ev1320qi evaluation board. complies with jedec ddr2 and ddr3 vddq tracking specification. 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 5 typical performance curves 80 82 84 86 88 90 92 94 96 98 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 efficiency (%) output current (a) efficiency vs. output current vtt = 0.9v vtt = 0.75v vtt = 0.6v conditions av in = 3.0v vddq = 2* vtt 80 82 84 86 88 90 92 94 96 98 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 efficiency (%) output current (a) efficiency vs. output current vtt = 0.9v vtt = 0.75v vtt = 0.6v conditions av in = 3.3v vddq = 2* vtt 80 82 84 86 88 90 92 94 96 98 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 efficiency (%) output current (a) efficiency vs. output current vtt = 0.9v vtt = 0.75v vtt = 0.6v conditions av in = 3.6v vddq = 2* vtt 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 vtt (v) vddq (v) output voltage vs. input voltage load = 0a load = 1a load = 2a conditions avin = 3.0v note: vtt is measured at bulk caps on evaluation board edge 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 vtt (v) vddq (v) output voltage vs. input voltage load = 0a load = 1a load = 2a conditions avin = 3.3v note: vtt is measured at bulk caps on evaluation board edge 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 vtt (v) vddq (v) output voltage vs. input voltage load = 0a load = 1a load = 2a conditions avin = 3.6v note: vtt is measured at bulk caps on evaluation board edge 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 6 typical performance curves (continued) 0.54 0.55 0.56 0.57 0.58 0.59 0.60 0.61 0.62 0.63 0.64 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 vtt (v) output current (a) output voltage vs. output current ta = -45 c ta = 25 c ta = 85 c conditions av in = 3.3v vddq = 1.2v vtt = 0.6v note: vtt is measured at bulk caps on evaluation board edge 0.70 0.71 0.72 0.73 0.74 0.75 0.76 0.77 0.78 0.79 0.80 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 vtt (v) output current (a) output voltage vs. output current ta = -45 c ta = 25 c ta = 85 c conditions av in = 3.3v vddq = 1.5v vtt = 0.75v note: vtt is measured at bulk caps on evaluation board edge 0.84 0.85 0.86 0.87 0.88 0.89 0.90 0.91 0.92 0.93 0.94 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 vtt (v) output current (a) output voltage vs. output current ta = -40 c ta = 25 c ta = 85 c conditions av in = 3.3v v ddq = 1.8v conditions av in = 3.3v v ddq = 1.8v vtt = 0.9v note: vtt is measured at bulk caps on evaluation board edge 0.50 0.52 0.54 0.56 0.58 0.60 0.62 0.64 0.66 0.68 0.70 -40 -15 10 35 60 85 vtt (v) ambient temperature ( c) output voltage vs. temperature load = 0a load = 1a load = 2a conditions avin=3.3v vddq = 1.2v note: vtt is measured at bulk caps on evaluation board edge 0.65 0.67 0.69 0.71 0.73 0.75 0.77 0.79 0.81 0.83 0.85 -40 -15 10 35 60 85 vtt (v) ambient temperature ( c) output voltage vs. temperature load = 0a load = 1a load = 2a conditions avin=3.3v vddq = 1.5v note: vtt is measured at bulk caps on evaluation board edge 0.80 0.82 0.84 0.86 0.88 0.90 0.92 0.94 0.96 0.98 1.00 -40 -15 10 35 60 85 vtt (v) ambient temperature ( c) output voltage vs. temperature load = 0a load = 1a load = 2a conditions avin=3.3v vddq = 1.8v note: vtt is measured at bulk caps on evaluation board edge 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 7 typical performance curves (continued) 0 1 2 3 4 5 6 7 8 9 10 -40 -15 10 35 60 85 avin input current (ma) ambient temperature( c) avin input current vs. temperature avin = 3.6v avin = 3.3v avin = 3.0v conditions vddq = 1.5v vtt = 0.75v 0 1 2 3 4 5 6 7 8 9 10 -40 -15 10 35 60 85 avin input current (ma) ambient temperature( c) avin input current vs. temperature vddq = 1.2v vddq = 1.5v vddq = 1.8v conditions avin = 3.3v 200 300 400 500 600 700 800 900 1000 -40 -15 10 35 60 85 vddq input current (a) ambient temperature( c) vddq input current vs. temperature avin = 3.6v avin = 3.3v avin = 3.0v conditions vddq = 1.5v vtt = 0.75v no load 200 300 400 500 600 700 800 900 1000 -40 -15 10 35 60 85 vddq input current (a) ambient temperature( c) vddq input current vs. temperature vtt = 0.6v vtt = 0.75v vtt = 0.9v conditions avin = 3.3v vddq = 2*vtt no load 500 550 600 650 700 750 -40 -15 10 35 60 85 oscillator frequency (khz) ambient temperature( c) frequency vs. temperature avin = 3.6v avin = 3.3v avin = 3.0v conditions vddq = 1.5v vtt = 0.75v 10 100 1000 0.1 1 10 100 vtt rise time (s) ss capacitance (nf) vtt rise time vs. capacitance conditions vddq = 1.5v vtt = 0.75v 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 8 typical performance characteristics vout (ac coupled) output ripple at 1a load conditions avin = 3.3v vddq = 1.5v vtt = 0.75v cin=22f, cout=22f, c1p = 22f+1x10f load = 1a note: output ripple is measured at bulk capacitors on evaluation board edge 500mhz bandwidth vout (ac coupled) output ripple at 2a load conditions avin = 3.3v vddq = 1.5v vtt = 0.75v cin=22f, cout=22f, c1p = 22f+1x10f load = 2a note: output ripple is measured at bulk capacitors on evaluation board edge 500mhz bandwidth switching waveform at no load conditions avin = 3.3v, vddq = 1.5v, vtt = 0.75v, cin=22f, cout=22f, c1p = 22f+1x10f ch1:vddq ch2:c1p ch3:c1n ch4:vtt switching waveform at 500ma conditions avin = 3.3v, vddq = 1.5v, vtt = 0.75v, cin=22f, cout=22f, c1p = 22f+1x10f ch1:vddq ch2:c1p ch3:c1n ch4:vtt switching waveform at 1a conditions avin = 3.3v, vddq = 1.5v, vtt = 0.75v, cin=22f, cout=22f, c1p = 22f+1x10f ch1:vddq ch2:c1p ch3:c1n ch4:vtt switching waveform at 2a conditions avin = 3.3v, vddq = 1.5v, vtt = 0.75v, cin=22f, cout=22f, c1p = 22f+1x10f ch1:vddq ch2:c1p ch3:c1n ch4:vtt 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 9 typical performance characteristics (continued) vtt (ac coupled) load transient from 0 to 500ma conditions avin = 3.3v vddq = 1.5v vtt = 0.75v cin=22f, cout=22f c1p = 22f+1x10f) load vddq (ac coupled) ? vtt is due to ? vddq note: output deviation is measured at bulk capacitors on evaluation board edge vtt (ac coupled) load transient from 0 to 1a conditions avin = 3.3v vddq = 1.5v vtt = 0.75v cin=22f, cout=22f c1p = 22f+1x10f load vddq (ac coupled) ? vtt is due to ? vddq note: output deviation is measured at bulk capacitors on evaluation board edge vtt (ac coupled) load transient from 0 to 1.5a conditions avin = 3.3v vddq = 1.5v vtt = 0.75v cin=22f, cout=22f c1p = 22f+1x10f load vddq (ac coupled) ? vtt is due to ? vddq note: output deviation is measured at bulk capacitors on evaluation board edge vtt (ac coupled) load transient from 0 to 2a conditions avin = 3.3v vddq = 1.5v vtt = 0.75v cin=22f, cout=22f c1p = 22f+1x10f load vddq (ac coupled) ? vtt is due to ? vddq note: output deviation is measured at bulk capacitors on evaluation board edge vddq (ac coupled) vddq to vtt tracking with line conditions load = 1 avin = 3.3v, c in=22f, cout=22f, c1p = 22f+1x10f vtt (ac coupled) ? vtt is due to ? vddq enable startup with pok at no load vddq conditions no load css = 15nf avin = 3.3v, vddq = 1.2v, vtt = 0.6v, cin=22f, cout=22f, c1p = 22f+1x10f vtt p ok 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 10 typical performance characteristics (continued) enable startup with pok at 2a vddq conditions no load css = 15nf avin = 3.3v, vddq = 1.2v, vtt = 0.6v cin=22f, cout=22f c1p = 22f+1x10f vtt pok enable parallel operation startup at 4a vddq (vddq#1 tied to vddq#2) conditions load = 4a css = 15nf avin = 3.3v, vddq = 1.8v, vtt = 0.9v, cin=22f, cout=22f c1p = 22f+1x10f vtt (vtt#1 tied to vtt#2) total load = 4a (2a + 2a) parallel vddq startup with pok vddq (vddq#1 tied to vddq#2) conditions load = 4a, css = 15nf avin = 3.3v, vddq = 1.8v, vtt = 0.9v, cin=22f, cout=22f c1p = 22f+1x10f vtt (vtt#1 tied to vtt#2) pok #1 pok #2 parallel operation at 4a ch1: vddq (vddq#1 tied to vddq#2) ch2:vtt (vtt#1 tied to vtt#2) total load = 4a (2a + 2a) load #2: 2a load #1: 2a parallel operation load transient ch1: vddq (vddq#1 tied to vddq#2) conditions load = 4a avin = 3.3v, vddq = 1.5v, vtt = 0.75v, cin=22f, cout=22f c1p = 22f+1x10f ch2: vtt (vtt#1 tied to vtt#2) l oad ? v tt is due to ? vddq note: output deviation is measured at bulk capacitors on evaluation board edge 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 11 functional block diagram figure 4: functional block diagram 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 12 functional description vddq/vtt converter the ev1320qi is designed to replace low efficiency linear regulators as well as expensive switch-mode dcdc memory terminations. the patented ev1320qi architecture provides efficiencies up to 96% with a solution footprint similar to that of a linear regulator. vout (vtt) tracks ?vddq with 40mv accuracy and is compliant with ddr2/3/qdr and low power ddr4 jedec memory termination requirements. the ev1320qi tracks vddq directly so there is no need for a separate reference voltage or resistor divider network. if a vref signal is needed for the vtt termination, it can be generated by an external vref divider circuit from vddq, as shown in figure 5. the r vref resistors divide the vddq voltage by 2 and can be used as the vref signal. choose high accuracy resistors for r vref . if more current is needed for vref, the divider signal may be buffered by a voltage follower as shown in figure 5. be sure the r vref resistor values are negligible compared to the input impedance of the voltage follower to ensure vref voltage accuracy. figure 5 . vref divider external circuit soft-start operation the ev1320qi has a programmable soft-start. the ev1320 can operate with avin on, enable high, and vddq ramped up and down. if, however, vddq comes up first, and then the device is enabled, the soft-start capacitor limits the rise of the output (vtt). the output (vtt) ramp rate is determined by the value of the soft start (ss) capacitor, as shown in table 1. the soft-start time begins when enable crosses its threshold until vtt reaches final value. table 1. typical soft-start capacitance time table (no load) ss capacitance (nf) vtt rise time ( s) 27 450 15 265 6.8 140 2.7 70 1 40 0.47 30 0.27 25 0.1 20 note : if a fault condition occurs during normal operation the output is discharged through a 100 resistor for a period of 1.5ms and then a soft start cycle is initiated. enable operation the enable pin provides a means to enable or disable operation of the part. when enable is pulled high the device will go through a soft start sequence. when enable is pulled low such as if the memory device enters s3 (suspend to ram), the output will be discharged through a 100 resistor. please note that if the equivalent load resistance is lower than 100 , the output will discharge faster. the enable pin should not be left floating. power ok (pok) the ev1320qi provides an open drain output to indicate if the output voltage stays within nominally +/- 10% of vddq/2. within this range, the pok output is allowed to be pulled high. outside this range, pok remains low. however, during transitions such as enable/disable and fault restart the pok output will not change state until the transition is complete for enhanced noise immunity. the pok has 1ma sink capability for events where it needs to feed a device with standard cmos inputs. when pok is pulled high, the pin leakage current is as low as 25a maximum over temperature. this allows a large pull up resistor such as 100k to be used for minimal current consumption in shutdown mode. 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 13 over-current protection the overload function is achieved by sensing the output voltage. an overload state is entered when the device is out of soft start and the output voltage drops below ~85% of vddq/2. when an ocp condition is detected, the device is disabled, the output is discharged through a 100 resistor for a period of 1.5ms. after the 1.5ms discharge time has expired, a soft start is initiated as described in the soft start section. if an over current condition is again detected the device will repeat the discharge/soft start cycle in a hiccup manner as long as the over current condition persists. thermal overload protection thermal shutdown will disable operation when the junction temperature exceeds approximately 150oc. output will discharge through a 100 ohm resistor for 1.5ms. if the thermal fault condition is still present then the device will hiccup until temp falls by 25c. once the junction temperature drops by approximately 25oc, the converter will re-start with a normal soft-start. input under-voltage lock-out internal circuits ensure that the converter will not start switching until the avin voltage is above the specified minimum voltage. 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 14 application information figure 6. general application circuit for 2a operation general application circuit figure 6 shows a typical application circuit for the ev1320qi. the resistor before the avin capacitor is optional, but recommended if avin supply is noisy. note: the output filter capacitor section assumes that there is additional decoupling on the vtt island(s) of approximately 100f per amp of vtt current. if this vtt decoupling is not present, additional bulk capacitance will be required on the ev1320qi output. soft-start ramp rate is set by choice of the soft start capacitor (c ss ) as described in the soft start section. power up sequence during power up, neither enable nor vddq should be asserted before avin. there are two common acceptable turn-on/off sequences for the device. enable can be tied to avin and come up with it, and vddq can be ramped up and down as needed. in this case, the output will attempt to track vddq. alternatively, vddq can be brought high after avin is asserted, and the device can be turned on and off by toggling the enable pin. in this case, the output will ramp up as determined by the soft-start capacitor, and it will turn off as described in ?enable operation? section. input capacitors a 22f 4v x5r mlcc capacitor is required at the vddq input for 2a applications. a 10f may be used for under 1a applications. the input capacitor must be placed at the position closest to the vddq pins of the ev1320qi. either 0603 or 0805 case size is acceptable. the capacitors should be 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 15 connected between vddq pin and the pgnd pin. do not connect the capacitors to the agnd terminal. do not use y5v or equivalent dielectric capacitors. these capacitors lose substantial capacitance with bias, frequency, and temperature and are thus not appropriate for use in dcdc converter applications. refer to the ?layout recommendation? section for guidance on placement and pcb routing. table 1 . recommended capacitor configurations max i out cin cout cfly 1a 10 f 10 f 22f 2a 22 f 22 f 22f + 10f output capacitors a 22f 4v x5r mlcc capacitor is required at the output for 2a applications. a 10f may be used for under 1a applications. the output capacitor must be placed at the position closest to the vout pins of the ev1320qi. either 0603 or 0805 case size is acceptable. the capacitors should be connected between vout pin and the pgnd pin. do not connect the capacitors to the agnd terminal. do not use y5v or equivalent dielectric capacitors. these capacitors lose substantial capacitance with bias, frequency, and temperature and are thus not appropriate for use in dcdc converter applications. this capacitor recommendation assumes that there is additional bulk and decoupling capacitance at vtt dimm leads and the vtt islands. ensure that there is at least 100f of bulk capacitance per amp of vtt current. if there is not sufficient bulk capacitance, add additional bulk capacitance to the output of the ev1320qi. refer to the ?layout recommendation? section for guidance on placement and pcb routing. c1n and c1p capacitors (cfly) a 22f 4v x5r mlcc and a 10f 4v x5r mlcc capacitors must be connected between the c1n and c1p pins for 2a applications. a 22f may be used for under 1a applications. the cfly capacitor must be placed in the position closest to the c1n and c1p pins. the c1n and c1p pads should not be connected to any other plane or trace. capacitor case size of 0805 or 0603 is acceptable. do not use y5v or equivalent dielectric capacitors. these capacitors lose substantial capacitance with bias, frequency, and temperature and are thus not appropriate for use in dcdc converter applications. refer to the ?layout recommendation? section for guidance on placement and pcb routing. parallel operation the architecture of the ev1320qi lends itself to seamless parallel operation. up to 4 devices can be paralleled to achieve a vtt current of up to 8a. figure 7 shows an example circuit diagram for parallel operation of three ev1320qis. the following guidelines must be followed for proper parallel operation. 1. the vddq inputs should be connected to a common vddq bus. 2. the vout connections should be connected to a common vtt bus. 3. each ev1320qi device must have its own input and output capacitors connected close to the device as described in the input and output capacitor sections. the input and output capacitors should be connected to the local pgnd pins on the respective ev1320qi devices. 4. the c1n-c1p capacitors should only be connected to their respective ev1320qi devices. they should not be connected to any common bus, vin, vout, or any other signal or plane. 5. all avin connections should be tied to a common 3.3v supply rail. each ev1320qi should have its own avin filter resistor and capacitor if required. 6. all enable pins should be tied to a common enable signal. 7. all soft start pins should be tied together and a single soft start capacitor should be used. each device should not have its own soft start capacitor. 8. all analog ground (agnd) connections should be tied together. the single soft start capacitor should be connected to this common agnd. 9. all power ground (pgnd) connections should be tied together through a common pgnd plane. however, each input and output capacitor compliment should be connected to the local pgnd pins on each individual ev1320qi device. 10. the devices should be placed such that the impedance in each path to the load is equivalent to ensure current balance. 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 16 figure 7. parallel operation with three ev1320qi technical suport contact enpirion applications for additional support regarding the use of this product (techsupport@enpirion.com). 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 17 thermal considerations thermal considerations are important physical limitations that cannot be avoided in the real world. whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be accounted for. the enpirion ev1320qi vddq/vtt converter is packaged in a 3x3x0.55mm 16-pin qfn package. the recommended maximum junction temperature for continuous operation is 125c. continuous operation above 125c may reduce long-term reliability. the device has a thermal overload protection circuit designed to turn off the device at an approximate junction temperature value of 150c. the ev1320qi is guaranteed to support the full 2a output current up to 85c ambient temperature. the following example and calculations illustrate the thermal performance of the ev1320qi. example: vddq = 1.2v vtt = 0.6v i out = 2a first calculate the output power. p out = vtt * i out = 0.6v x 2a = 1.2w next, determine the input power based on the efficiency ( ) shown in figure 8. figure 8: efficiency vs. output current for vddq = 1.2v, vtt = 0.6v at 2a, 92.6% = p out / p in = 92.6% = 0.926 p in = p out / p in 1.2w / 0.926 1.2959w the power dissipation (p d ) is the power loss in the system and can be calculated by subtracting the output power from the input power. p d = p in ? p out 1.2959w ? 1.2w 0.0959w with the power dissipation known, the temperature rise in the device may be estimated based on the theta ja value ( ja ). the ja parameter estimates how much the temperature will rise in the device for every watt of power dissipation. the ev1320qi has a ja value of 50 oc/w without airflow. determine the change in temperature ( ? t) based on p d and ja . ? t = p d x ja ? t 0.0959w x 50c/w = 4.795c 4.8c the junction temperature (t j ) of the device is approximately the ambient temperature (t a ) plus the change in temperature. we assume the initial ambient temperature to be 25c. t j = t a + ? t t j 25c + 4.8c 29.8c with 0.0959w dissipated into the device, the t j will be 29.8c. the maximum operating junction temperature (t jmax ) of the device is 125c, so the device can operate at a higher ambient temperature. the maximum ambient temperature (t amax ) allowed can be calculated. t amax = t jmax ? p d x ja 125c ? 4.8c 120.2c the ambient temperature can actually rise by another 95.2c, bringing it to 120.2c before the device will reach t jmax . this indicates that the ev1320qi can support the full 2a output current range up to approximately 120.2c ambient temperature given the input and output voltage conditions. this allows the ev1320qi to guarantee full 2a output current capability at 85c with room for margin. note that the efficiency will be slightly lower at higher temperatures and these calculations are estimates. 80 82 84 86 88 90 92 94 96 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 efficiency (%) output current (a) efficiency vs. output current vtt = 0.6v conditions av in = 3.0v vddq = 2* vtt 92.6% 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 18 layout recommendation figure 9: typical top side and bottom side layout recommendation (top view) figure 9 shows the critical components along with top and bottom traces of a recommended minimum footprint ev1320qi layout with enable tied to vddq. alternate enabling configurations, and the pok pin would have to be connected and routed according to the specific customer application. please see the gerber files at www.enpirion.com for exact dimensions and the internal layers. recommendation 1: input and output filter capacitors should be placed on the same side of the pcb, and as close to the ev1320qi package as possible. they should be connected to the device with very short and wide traces. do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. the +v and gnd traces between the capacitors and the ev1320qi should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. recommendation 2 : the c1n-c1p capacitors should be placed as close to the c1n-c1p pins as possible. use large copper planes to minimize resistance and inductance. the c1p and c1n traces between the capacitors and the ev1320qi should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. recommendation 3: the system ground plane should be the first layer immediately below the surface layer (layer 2). this ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. recommendation 4 : the vddq and vout copper are paralleled on layers 3 and 4 in order to minimize overall series resistance. please see gerber files. recommendation 5 : avin is the power supply for the internal control circuits. it should be connected to the 3.3v bus at a quiet point. a 10f bypass capacitor (shown on the backside in figure 9) is needed on the avin node. if the avin supply is noisy, an optional 1 resistor is recommended in series with avin. see figure 6. recommendation 6 : the agnd pin does not get connected to pgnd on layer 1. it connects to pgnd on layer 2 ground plane. this provides some noise isolation between agnd and the noisy pgnd trace on layer 1. recommendation 7 : the soft-start capacitor css and the avin capacitor cavin are placed on the back side in figure 9 so that the input pgnd trace is not compromised. recommendation 8 : if pok needs to be used, place a via to the left of pin 4, and route the pok trace on layer 3 to the pok resistor. place the pok resistor to avin such that any modifications to the traces and placements in this recommended layout are minimized. recommendation 9 : follow all the layout recommendations as close as possible to optimize performance. enpirion provides schematic and layout reviews for all customer designs. please contact techsupport@enpirion.com for enpirion applications engineering support. 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 19 recommended pcb footprint figure 10: ev1320qi pcb footprint (top view) 06831 april 9, 2012 rev: c
ev1320qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 20 package and mechanical figure 11: ev1320qi package dimensions (bottom view) contact information enpirion, inc. perryville iii corporate park 53 frontage road - suite 210 hampton, nj 08827 usa phone: 1.908.894.6000 fax: 1.908.894.6090 enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. information furnished by enpirion is believed to be accurate and reliable. enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may result from its use. enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment used in hazardous environment without the express written authority from enpirion 06831 april 9, 2012 rev: c

▲Up To Search▲

Price & Availability of EV1320QI-E

	To Download EV1320QI-E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .